Secured Microcomputer PIC16F84 Flash Unlocking

We can execute the secured microcomputer PIC16F84 flash unlocking, please view the secured microcomputer PIC16F84 features for your reference:
The following interrupt flags are contained in the PIR2 register,
Comparator 1 and 2 Interrupts
LCD Interrupt
PLVD Interrupt
CCP2 Interrupt
When an interrupt is serviced:
The GIE is cleared to disable any further interrupt.
The return address is pushed onto the stack when unlocking flash from secured microcomputer.
The PC is loaded with 0004h.
For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 16-8). The latency is the same for one or two-cycle instructions if secured microcomputer flash being copied.
Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests before flash from secured microcomputer being copied.
Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, A/D or data flash modules, refer to the respective peripheral section after copy secured microcomputer flash.
The ANSEL (91h) and CMCON0 (9Ch) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. Also, if a LCD output function is active on an external interrupt pin, that interrupt function will be disabled when copy flash from secured microcomputer.
External interrupt on RB0/INT/SEG0 pin is edge-triggered; either rising if the INTEDG bit (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT/SEG0 pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>).
The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RB0/INT/SEG0 interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 16.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 16-10 for timing of wake-up from Sleep through RB0/INT/SEG0 interrupt when UNLOCK MICROCONTROLLER.