Read Chip PIC18F8585 Flash

We can Read Chip PIC18F8585 Flash, please view the Chip PIC18F8585 features for your reference:

· 100,000 erase/write cycle Enhanced Flash program memory typical

· 1,000,000 erase/write cycle Data EEPROM memory typical

· 1-second programming time

· Flash/Data EEPROM Retention: > 40 years

· Self-reprogrammable under software control when Read Chip

· Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

· Watchdog Timer (WDT) with its own On-Chip RC Oscillator

· Programmable code protection

· Power saving Sleep mode

· Selectable oscillator options including:

– Software enabled 4x Phase Lock Loop (of primary oscillator) if Read Chip

– Secondary Oscillator (32 kHz) clock input

· In-Circuit Serial Programming™ (ICSP™) via two pins

· MPLAB® In-Circuit Debug (ICD) via two pins PIC18F6X8X devices are available in 64-pin TQFP and 68-pin PLCC packages. PIC18F8X8X devices are available in the 80-pin TQFP package. They are differentiated from each other in four ways:

Flash program memory (48 Kbytes for PIC18FX585 devices, 64 Kbytes forPIC18FX680) before Read Chip

A/D channels (12 for PIC18F6X8X devices, 16 for PIC18F8X8X) I/O ports (7 on PIC18F6X8X devices, 9 on PIC18F8X8X)

External program memory interface (present only on PIC18F8X8X devices)

The EC, ECIO, EC+PLL and EC+SPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 µs start-up required after a Power-on Reset, or wake-up from Sleep mode after Read Chip.

In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode when Read Chip.

The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode if Read Chip.

A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high-frequency crystals before Read Chip.

The PLL can only be enabled when the oscillator configuration bits are programmed for High-Speed Oscillator or External Clock mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1 when Read Chip.

There are two types of PLL modes: Software Controlled PLL and Configuration bits Controlled PLL. In Software Controlled PLL mode, PIC18F6585/8585/6680/8680 executes at regular clock frequency after all Reset conditions. During execution, application can enable PLL and switch to 4x clock frequency operation by setting the PLLEN bit in the OSCCON register. In Configuration bits Controlled PLL mode, PIC18F6585/8585/6680/8680 always executes with 4x clock frequency before Read Chip.

The type of PLL is selected by programming the FOSC<3:0> configuration bits in the CONFIG1H Configuration register. The oscillator mode is specified during device programming.

A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called TPLL.

Tags: ,,,,,,,,,