Extract PLD IC PALCE16V8


We can extract PLD IC PALCE16V8, please view below chip features for your reference:



· Active pull-up on data input pins

· Low power version (16V8L)

— 55 mA max. commercial (10, 15, 25 ns)

— 65 mA max. industrial (10, 15, 25 ns)

— 65 mA military (15 and 25 ns)

· Standard version has low power

— 90 mA max. commercial (10, 15, 25 ns)

115 mA max. commercial (7 ns)

— 130 mA max. military/industrial (10, 15, 25 ns)

· CMOS Flash technology for electrical erasability and reprogrammability

· PCI compliant

· User-programmable macrocell

— Output polarity control

Individually selectable for registered or combinatorial operation

· Up to 16 input terms and 8 outputs

· 7.5 ns com’l version

5 ns tCO

5 ns tS

7.5 ns tPD

125-MHz state machine

· 10 ns military/industrial versions

7 ns tCO

10 ns tS

10 ns tPD

62-MHz state machine

· High reliability

— Proven Flash technology

— 100% programming and functional testing

Functional Description

The Cypress PALCE16V8 is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell.

Functional Description (continued)

The PALCE16V8 is executed in a 20-pin 300-mil molded DIP, a 300-mil cerdip, a 20-lead square ceramic leadless chip car-

rier, and a 20-lead square plastic leaded chip carrier. The device provides up to 16 inputs and 8 outputs. The PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 20-pin PLDs such as 16L8, 16R8, 16R6, and 16R4.

The PALCE16V8 features 8 product terms per output and 32 input terms into the AND array. The first product term in a mac-

rocell can be used either as an internal output enable control or as a data product term.

There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macrocells and

16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or

combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled,

functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself.

Configuration Table 

Power-Up Reset

All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associ-

ated output pin will be HIGH due to active-LOW outputs.

Electronic Signature

An electronic signature word is provided in the PALCE16V8 that consists of 64 bits of programmable memory that can con-

tain user-defined data.

Security Bit

A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed.

Low Power

The Cypress PALCE16V8 provides low-power operation through the use of CMOS technology, and increased testability

with Flash reprogrammability.

Product Term Disable

Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individ-

ually disabled.

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