Extract IC PIC18F6310 Flash

We can Extract IC PIC18F6310 Flash, please view the IC PIC18F6310 features for your reference:


Power Managed Modes:

Run: CPU on, peripherals on

Idle: CPU off, peripherals on

Sleep: CPU off, peripherals off

Idle mode currents down to 5.8 µA typical

Sleep mode currents down to 0.1 µA typical when Extract IC

Timer1 Oscillator: 1.8 µA, 32 kHz, 2V

Watchdog Timer: 2.1 µA

Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

· Four Crystal modes:

– LP: up to 200 kHz if Extract IC

– XT: up to 4 MHz

– HS: up to 40 MHz

– HSPLL: 4-10 MHz (16-40 MHz internal)

· 4x Phase Lock Loop (available for crystal and internal oscillators)

· Two External RC modes, up to 4 MHz after Extract IC

· Two External Clock modes, up to 40 MHz

· Internal oscillator block:

– 8 user selectable frequencies, from 31 kHz to 8 MHz

– Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL

– User-tunable to compensate for frequency drift after Extract IC

· Secondary oscillator using Timer1 @ 32 kHz

· Fail-Safe Clock Monitor:

– Allows for safe shut down of device if primary or secondary clock fails

External Memory Interface (PIC18F8310/8410 Devices only):

· Address capability of up to 2 Mbytes after Extract IC

· 16-bit/8-bit interface

High current sink/source 25 mA/25 mA

Four external interrupts

Four input change interrupts

Four 8-bit/16-bit Timer/Counter modules

Up to 3 Capture/Compare/PWM (CCP) modules

Master Synchronous Serial Port (MSSP) module before Extract IC

supporting 3-wire SPI™ (all 4 modes) and I2C™

Master and Slave modes

Addressable USART module:

– Supports RS-485 and RS-232 Enhanced Addressable USART module:

– Supports RS-485, RS-232 and LIN 1.2 if Extract IC

– Auto-Wake-up on Start bit

– Auto-Baud Detect 10-bit, up to 12-channel Analog-to-Digital Converter module (A/D):

– Auto-acquisition capability

– Conversion available during Sleep Dual analog comparators with input multiplexing

Special Microcontroller Features: 

· C compiler optimized architecture:

– Optional extended instruction set designed to optimize re-entrant code if Extract IC

· 1000 erase/write cycle Flash program memory typical

· Flash Retention: 100 years typical

· Priority levels for interrupts

· 8 x 8 Single-Cycle Hardware Multiplier

· Extended Watchdog Timer (WDT):

– Programmable period from 4 ms to 131s when Extract IC

– 2% stability over VDD and temperature

· In-Circuit Serial Programming™ (ICSP™) via two pins

· In-Circuit Debug (ICD) via two pins

· Wide operating voltage range: 2.0V to 5.5V before Extract IC

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