Extract Chip PIC18F4523 Program

We can Extract Chip PIC18F4523 Program, please view the Chip PIC18F4523 features for your reference:

For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors:

· supply voltage

· values of the external resistor (REXT) and capacitor (CEXT) when Extract Chip

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator.

· operating temperature if Extract Chip

Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as:

· normal manufacturing variation

· difference in lead frame capacitance between package types (especially for low CEXT values)

· variations within the tolerance of limits of REXT and CEXT before Extract Chip

In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected.

A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator before Extract Chip.

The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode after Extract Chip.

The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 Configuration bits are programmed for HSPLL mode (= 0110).

The PLL is also available to the internal oscillator block when the INTOSC is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz if Extract Chip.

The operation of INTOSC with the PLL is described in Section 2.6.4 “PLL in INTOSC Modes”.

The PIC18LF2423/2523/4423/4523 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins when Extract Chip.

The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected, and can provide 31 kHz if required.

The other clock source is the internal RC oscillator (INTRC) which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled:

· Power-up Timer

· Fail-Safe Clock Monitor

· Watchdog Timer when Extract Chip

These features are discussed in greater detail in Section 23.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 30).

Additionally, the 31 kHz clock can be provided by either the INTOSC, or INTRC clock sources, depending on the INTSRC bit (OSCTUNE<7>) before Extract Chip.


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