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Features

· 5 ns pin-to-pin logic delays

· System frequency up to 178 MHz

· 72 macrocells with 1,600 usable gates

Available in small footprint packages

– 44-pin PLCC (34 user I/O pins)

– 44-pin VQFP (34 user I/O pins)

– 48-pin CSP (38 user I/O pins)

– 64-pin VQFP (52 user I/O pins)

– 100-pin TQFP (72 user I/O pins)

– Pb-free available for all packages

Product Specification

cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power.

– Low power operation

– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

– 3.3V or 2.5V output capability

– Advanced 0.35 micron feature size CMOS

Advanced system features

– In-system programmable

– Superior pin-locking and routability with Fast CONNECT™ II switch matrix

– Extra wide 54-input Function Blocks

– Up to 90 product-terms per macrocell with individual product-term allocation

– Local clock inversion with three global and one product-term clocks

– Individual output enable per output pin

– Input hysteresis on all user and boundary-scan pin inputs

– Bus-hold circuitry on all user pin inputs

– Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

– Endurance exceeding 10,000 program/erase cycles

– 20 year data retention

– ESD protection exceeding 2,000V

Pin-compatible with 5V-core XC9572 device in the

Copy CPLD IC Chip Xilinx XC9572XL-10TQG100C

For a general estimate of ICC, the following equation may be used:

ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP

+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f

where:

MCHS = # macrocells in high-speed configuration

PTHS = average number of high-speed product terms per macrocell

MCLP = # macrocells in low power configuration

PTLP = average number of low power product terms per macrocell

f = maximum clock frequency

MCTOG = average % of flip-flops toggling per clock (~12%)

This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled.

The actual ICC value varies with the design application and should be verified during normal system operation when Copy CPLD IC Chip Xilinx XC9572XL-10TQG100C. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx 44-pin PLCC package and the 100-pin TQFP package