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Break Altera CPLD EPM7064LC68-15
Break Altera CPLD EPM7064LC68-15
We can Break Altera CPLD EPM7064LC68-15, please view below CPLD features for your reference:
Features
High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
PCI-compliant devices available
Altera Corporation
DS-MAX7000-6.7
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or theMAX 7000B Programmable Logic Device Family Data Sheet.